In the fabrication of field-effect transistors (FETs) with self-aligned gates, it has been a common practice to use an insulated gate structure in conjunction with the field oxide of a device as the mask for the formation of the source and drain regions thereof. This process allows precise positioning of the source and drain regions of a device with respect to the channel over which the gate electrode exerts its effect and thus avoids undesirable effects such as stray capacitance and ohmic and non-ohmic losses. These self-aligned gate processes have been carried out using both solid state diffusion and ion implantation, as described respectively by H. G. Dill in U.S. Pat. No. 3,544,399 and by R. W. Bower in U.S. Pat. No. 3,472,712, both assigned to the present assignee. After the source and drain regions of a self-aligned gate FET have been established and a surface passivation layer formed thereon, holes are etched in the passivation layer covering these regions using established masking procedures to define and limit the size of the contact holes. Finally, the metal contacts are established using well-known photoresist lift-off techniques which include forming a resist pattern, depositing the metal layer over the resist pattern and then removing the resist pattern to remove portions of the metal layer thereon.
During the prior art formation of the source and drain regions for these insulated-gate FETs, it is customary to use one set of photoresist masking steps to define the lateral extent of these regions. This may be accomplished by using the photoresist mask as an ion-implantation mask per se, or as a means of defining (by etching) the necessary ion implantation mask in another surface material. In either case, in order to properly make the necessary subsequent direct ohmic contacts to these source and drain regions with a chosen metallization pattern and insure that such contacts are sufficiently within the lateral boundaries of these source and drain regions to avoid metallization overlap on the source and drain junctions, it becomes necessary to closely align a second photoresist mask with these previously formed source and drain regions and insure that the etch openings in the second photoresist mask (required for SiO.sub.2 removal) are sufficiently within the lateral boundaries of the source and drain regions to prevent PN junction shorting. Since it is known that these mask-to-mask alignment tolerances may cause a variation of as much as 50% in the planar dimensions of the contact area, and since there is a minimum required source and drain silicon surface ohmic contact area corresponding to given current and power requirements of a particular device, these mask-to-mask alignment tolerances impose a limit on the size reduction of devices made by this prior art process. To a large degree, this size reduction limitation establishes or limits the maximum achievable operating or cut-off frequency for these devices. It is the removal of this latter limitation to which the present invention is directed.